The invention relates generally to automatic test equipment and more particularly a high speed and high accuracy power supply for use with a semiconductor tester to provide precise voltage levels to a high-speed device-under-test (DUT).
Semiconductor device manufacturing typically includes test processes at both the wafer and packaged-device levels. The testing is normally carried out by automatic test equipment (ATE) that simulates a variety of operating conditions to verify the functionality of each device. As is well known in the art, semiconductor devices generally require a source of power in order to function.
One function that the ATE often performs involves supplying power to the devices-under-test (DUTs). This is typically carried out by a DUT power supply mounted in the tester. The power supply also performs the dual function of measuring the power it supplies to the DUT. This includes current measurements under a variety of conditions. Consequently, to maintain precision and accuracy over time, the power supply typically undergoes periodic calibration.
Conventionally, calibrating the current measurement circuitry for a DUT power supply involves the use of external National Institute for Standards Traceability (NIST) components to establish the calibration gain and offset values. The standards typically comprise known precision resistors mounted to a customized calibration device-interface-board (DIB). A calibration DIB is not part of the tester, but rather a board assembly for a device handler (or prober) that couples to the tester. The power supply current is driven through the custom DIB resistors and the voltage across the resistors measured by a NIST compliant voltmeter. The current value calculated from the measured voltage and the measured resistors is then compared with the current value determined by the current measurement circuitry internal to the power supply. The differences are identified and calibration terms generated to compensate for the detected differences.
While this method generally works well for its intended applications, the use of the customized calibration DIB in order to calibrate the power supply current measurement circuitry usually involves xe2x80x9cundockingxe2x80x9d the tester from the DUT handler or prober, to effect the removal and subsequent replacement of the production device DIB. This can be a time-consuming process and often causes lost productivity in a manufacturing test environment.
In addition to requiring periodic calibration, a DUT power supply often undergoes validation procedures to ensure acceptable dynamic operation prior to engaging in production device testing. Validation generally involves steps to confirm that the power supply generates the requisite current, performs as expected under a wide range of dynamic conditions, and maintains stability. Similar to the calibration procedures described above, conventional validation procedures typically employ the use of a customized DIB. For the reasons explained with respect to custom calibration DIBs, undocking the tester to utilize a custom validation DIB is equally undesirable.
What is needed and heretofore unavailable is a high-accuracy DUT power supply capable of addressing the calibration and validation problems without the need to undock the tester. The DUT power supply of the present invention satisfies this need.
The DUT power supply of the present invention provides a way to conveniently and cost-effectively calibrate and validate a DUT power supply without undocking the tester from the device-under-test handler or prober. This minimizes tester down-time, correspondingly maximizing device throughput for semiconductor manufacturers.
To realize the foregoing advantages, the invention in one form comprises a power supply for use with a semiconductor tester to power a device-under-test. The power supply includes a housing and power circuitry disposed within the housing to generate power for the device-under-test. Internal load circuitry is disposed within the housing and coupled to the power circuitry to selectively simulate the electrical loading of a device-under-test on the power supply.
In another form, the invention comprises automatic test equipment for testing a device-under-test. The automatic test equipment includes a computer workstation and a test head coupled to the computer workstation. The test equipment further includes a device-under-test power supply including a housing and power circuitry disposed within the housing to generate power for the device-under-test. Internal load circuitry is disposed within the housing and coupled to the power circuitry to selectively simulate the electrical loading of a device-under-test on the power supply.
In yet another form the invention comprises a method of calibrating an ATE power supply current measurement unit without undocking a semiconductor tester from a device handling apparatus. The method includes the steps of selecting an in-tester load having a known impedance; substituting the device-under-test with the in-tester load, such that the ATE power supply current measurement unit is coupled to the in-tester load; measuring a first current with the current measurement unit; determining a second current by detecting the voltage across the in-tester load, and dividing the voltage value by the known impedance; comparing the first current to the second current to calculate an offset current; and assigning calibration values to compensate for the calculated offset current.
A further form of the invention comprises a method of validating a DUT power supply without undocking a semiconductor tester from a device handling apparatus. The method includes the steps of selecting a dynamic in-tester load having variable dynamic load characteristics; substituting the device-under-test with the in-tester load, such that the DUT power supply is coupled to the in-tester load; driving the dynamic in-tester load with the DUT power supply; and confirming that the DUT power supply operated within predetermined performance parameters during the driving step.
Other features and advantages of the present invention will be apparent from the following detailed description when read in conjunction with the accompanying drawings.